Wideband Predistortion for Efficient Power Amplifiers
Dr. Dang-Kièn Germain Pham
Telecom ParisTecH
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Prof. Patricia Desgreys
TELECOM PARISTECH
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Abstract
For three decades, the exchange rates in telecommunication standards have been exponentially increasing thanks to major innovations integrated from one generation to the following. The 5th generation of mobile standards 5G will, as its predecessors, provide a large increase of the data rates that will be made possible thanks to larger transmission bandwidths (up to several hundred of MHz) and to modulation schemes with higher spectral efficiency such as OFDMA and M-QAM. However, the novelty for 5G is the will to drastically minimize the power consumption with an objective of improving by 90% the energy efficiency compared to LTE standard. To achieve this objective, optimizations and innovations will be integrated at the different layers and levels of the communication systems.
For the physical layer and more specifically both for the mixed signal and RF part, the power consumption should be also minimized. In the transceiver, the most power consuming component is the power amplifier (PA) and classically there is a trade-off between PA’s efficiency and its linear behavior. In order to relax the design constraints due to this trade-off and to improve linearity and power efficiency, predistortion has emerged as a go-to solution. A digital predistortion (DPD) system is conventionally composed of a digital predistorter in the transmission path in charge of applying the inverse non-linear (NL) transfer characteristic so that combined with the PA, the overall transfer characteristic is linear. The adjustment of the predistorter coefficients should be done continuously or regularly to compensate for process, voltage and temperature (PVT) variations of the PA and therefore requires an observation path.
In 5G, the main challenges for the predistortion technique are the higher peak to average power ratio (PAPR) of the new modulation schemes and the large signal bandwidth which has grown to several hundred MHz. The combination of these two effects leads to higher constraints on :
For three decades, the exchange rates in telecommunication standards have been exponentially increasing thanks to major innovations integrated from one generation to the following. The 5th generation of mobile standards 5G will, as its predecessors, provide a large increase of the data rates that will be made possible thanks to larger transmission bandwidths (up to several hundred of MHz) and to modulation schemes with higher spectral efficiency such as OFDMA and M-QAM. However, the novelty for 5G is the will to drastically minimize the power consumption with an objective of improving by 90% the energy efficiency compared to LTE standard. To achieve this objective, optimizations and innovations will be integrated at the different layers and levels of the communication systems.
For the physical layer and more specifically both for the mixed signal and RF part, the power consumption should be also minimized. In the transceiver, the most power consuming component is the power amplifier (PA) and classically there is a trade-off between PA’s efficiency and its linear behavior. In order to relax the design constraints due to this trade-off and to improve linearity and power efficiency, predistortion has emerged as a go-to solution. A digital predistortion (DPD) system is conventionally composed of a digital predistorter in the transmission path in charge of applying the inverse non-linear (NL) transfer characteristic so that combined with the PA, the overall transfer characteristic is linear. The adjustment of the predistorter coefficients should be done continuously or regularly to compensate for process, voltage and temperature (PVT) variations of the PA and therefore requires an observation path.
In 5G, the main challenges for the predistortion technique are the higher peak to average power ratio (PAPR) of the new modulation schemes and the large signal bandwidth which has grown to several hundred MHz. The combination of these two effects leads to higher constraints on :
- The compensation blocks (estimator + predistorter) because of the large growth of the number of coefficients required to properly linearize PAs that are expected to exhibit more nonlinearities and memory effects.
- The data converters (Digital to Analog Converter (DAC) + Analog to Digital Converter (ADC)) because they have to process a very wideband signal which is composed of the main signal plus the intermodulation products components.
History, Motivation and Focus
The tutorial will cover all the material from basics to advanced techniques of predistortion. The two first sections introduce the most common approaches for PA modeling and for computing predistorter models. The third and fourth sections discuss in detail the implementation of the predistortion for RF transmitter highlighting the advantages and drawbacks of digital and analog approaches. The last section elaborates on the main issues to implement predistortion techniques for future wideband communication systems and highlights promising solutions addressing the identified limitations.
The tutorial will cover all the material from basics to advanced techniques of predistortion. The two first sections introduce the most common approaches for PA modeling and for computing predistorter models. The third and fourth sections discuss in detail the implementation of the predistortion for RF transmitter highlighting the advantages and drawbacks of digital and analog approaches. The last section elaborates on the main issues to implement predistortion techniques for future wideband communication systems and highlights promising solutions addressing the identified limitations.
Speakers
• Dr. Dang-Kièn Germain Pham
• Prof. Patricia Desgreys
Basic Structure of the Tutorial
Part 1: Non-Linear Modeling of PA for predistortion
- Memory less models
- Memory models
- Volterra series, Narmax
- Non parametric models : Neural Network
Part 2: Digital compensation of NL distortion
- Direct learning architecture : Identification, Inversion
- Indirect learning architecture : Nonlinear system inverse estimation
- Numerical instability
Part 3: Digital Predistortion techniques
- BS transmitter using DPD system
- Memory-Unaware DPD
- Memory-Aware DPD
- Advantages/disadvantages of DPD architectures
Part 4: Analog Radio Frequency Predistortion
- Memory-Unaware ARFPD
- Memory-Aware ARFPD
- Advantages/disadvantages of ARFPD architectures
- Comparison between DPD and ARFPD
- Mixed-Signal Predistorter
Part 5: ADC & estimation in the observation path
- SoA/Challenges
- Multi Stage Noise Band Cancellation ΣΔ ADC
- FFT-Based DPD Technique using Reduced Rate Subband Signals
• Dr. Dang-Kièn Germain Pham
• Prof. Patricia Desgreys
Basic Structure of the Tutorial
Part 1: Non-Linear Modeling of PA for predistortion
- Memory less models
- Memory models
- Volterra series, Narmax
- Non parametric models : Neural Network
Part 2: Digital compensation of NL distortion
- Direct learning architecture : Identification, Inversion
- Indirect learning architecture : Nonlinear system inverse estimation
- Numerical instability
Part 3: Digital Predistortion techniques
- BS transmitter using DPD system
- Memory-Unaware DPD
- Memory-Aware DPD
- Advantages/disadvantages of DPD architectures
Part 4: Analog Radio Frequency Predistortion
- Memory-Unaware ARFPD
- Memory-Aware ARFPD
- Advantages/disadvantages of ARFPD architectures
- Comparison between DPD and ARFPD
- Mixed-Signal Predistorter
Part 5: ADC & estimation in the observation path
- SoA/Challenges
- Multi Stage Noise Band Cancellation ΣΔ ADC
- FFT-Based DPD Technique using Reduced Rate Subband Signals
References
- V. N. Manyam, D.-K. G. Pham, C. Jabbour et P. Desgreys, “A low-power high-performance digital predistorter for wideband power amplifier”, Analog Integrated Circuits and Signal Processing, Springer US, accepted, to be published in July 2018.
- D.-K. G. Pham, G. Gagnon, F. Gagnon, G. Kaddoum C. Jabbour and P. Desgreys, “FFT-Based Limited Subband Digital Predistortion Technique for Ultra Wideband 5G Systems”, ”, 16th IEEE International New Circuits and Systems Conference (NEWCAS), Montréal, Canada, June 2018.
- V. N. Manyam, D.-K. G. Pham, C. Jabbour et P. Desgreys, “A Wideband Mixed-Signal Predistorter for Small-Cell Base Station Power Amplifiers”, IEEE International Symposium on Circuits and Systems ISCAS2018, Firenze, May 2018.
- P. Desgreys, V. N. Manyam, K. Tchambake, D.-K. G. Pham et C. Jabbour, “Wideband Power Amplifier Predistortion: Trends, Challenges and Solutions”, 12th IEEE International Conference on ASIC (ASICON), Guiyang, China, October 2017.
- V. N. Manyam, D.-K. G. Pham, C. Jabbour et P. Desgreys, “An FIR Memory Polynomial Predistorter for Wideband RF Power Amplifiers”, 15th IEEE International New Circuits and Systems Conference (NEWCAS), Strasbourg, France, June 2017.
- D.-K. G. Pham, G. Gagnon, F. Gagnon, P. Desgreys and P. Loumeau, “Hardware implementation of subsampled adaptive subband digital predistortion algorithm”, Analog Integrated Circuits and Signal Processing, Springer US, DOI: 10.1007/s10470-016-0791-4, pp. 1-9, July 2016.
- K. Tchambake, D.-K. G. Pham, C. Jabbour, P. Desgreys and P. Loumeau, “A multi-channel ΣΔ modulator for subband digital predistortion with LTE signals”, 14th IEEE International New Circuits and Systems Conference (NEWCAS), Vancouver, Canada, June 2016.
- D.-K. G. Pham, G. Gagnon, F. Gagnon, P. Desgreys and P. Loumeau, “A Subsampled Adaptive Subband Digital Predistortion Algorithm”, IEEE Int. Conf. NEWCAS, Trois-Rivières, Canada, June 2014.
- D.-K. G. Pham, P. Desgreys, M. Abi Hussein, P. Loumeau, O. Venard, “Impact of Subband Quantization on DPD Correction Performance”, IEEE Int. Conf. On Electronics, Circuits and Systems (ICECS), Abu Dhabi, UAE, Dec. 2013.
- D.-K. G. Pham, P. Desgreys, P. Loumeau, T. Ridgers and G. Monnerie, “High-Level Synthesis of General Multi-Stage Noise Band Cancellation ΣΔ ADC”, Analog Integrated Circuits and Signal Processing, Springer Ed., DOI: 10.1007/s10470-013-0148-1, pp 1-11, Sept. 2013.
- D.-K. G. Pham, P. Desgreys, P. Loumeau and T. Ridgers, “Optimized New ADC Architecture Using SD Modulators for Nonlinearly Distorted Signals”, IEEE International NEWCAS Conference, Montreal, Canada, June 2012.
- D.-K. G. Pham, P. Desgreys, P. Loumeau and T. Ridgers, “Multi-Stage Noise Band Cancellation ΣΔ Modulator for the digitization of distorted signals”, Electronics Letters, vol. 48, no. 10, May 2012.
- D.-K. G. Pham, P. Desgreys, P. Loumeau and T. Ridgers, “Method for Multiband Multilevel Analog-to-Digital Conversion”, patent n° EG/VP-FR 12 53436, April 2012.
Dang-Kièn Germain Pham received the Electrical Engineering, Computer Science and Telecommunications master's degree from the Ecole Nationale Supérieure de l'Électronique et de ses Applications (ENSEA) and the Master Degree in Intelligent and Communicating Systems from the University of Cergy-Pontoise (UCP) in 2009.
In 2013, he received the Ph.D. degree in Electronics and Communications at Telecom ParisTech, Paris, France. He did a post-doctorate at École de technologie supérieure, Montréal, Canada during 2014 and now he is a research engineer at Telecom ParisTech. His research interests include sigma delta modulation and digital processing for power amplifier linearization.
Patricia Desgreys received the M.Sc. degree and Ph.D. in Microelectronics from the University of Bordeaux in 1996 and 1999 respectively. She has been with Institute Mines Telecom - TELECOM ParisTech since 2000. She is currently full professor heading the Circuit and Communication Systems (C2S) research team at the LTCI Laboratory. She is in charge of research on Wireless Systems and Design Techniques for Nanoscale Circuits with special emphasis on Cognitive Radio Systems, Smart AMS Systems for IoT & Cyber-Physical Systems. So far, she has co-authored more than 120 technical publications mainly in international journals and conference proceedings and has been involved in many collaborative projects. Since 2007, she is a member of the Steering Committee (SC) of French research network GdR SOC2 in charge of animating the community of 600 French researchers on SoC design for embedded systems and connected objects. She is involved in the international animation of the CAS community, in particular President of IEEE-CAS France since 2015, member of IEEE NEWCAS Steering Committee since 2011, Technical Program Chair (TPC) of IEEE NEWCAS in 2012 & 2013 and TPC of IEEE ICECS on 2016. She has been Guest Editor of Special Issues in Analog Integrated Circuits and Signal Processing in 2013 & 2014 and she is currently guest editor of the ISICAS special issue in IEEE TCASII journal.
In 2013, he received the Ph.D. degree in Electronics and Communications at Telecom ParisTech, Paris, France. He did a post-doctorate at École de technologie supérieure, Montréal, Canada during 2014 and now he is a research engineer at Telecom ParisTech. His research interests include sigma delta modulation and digital processing for power amplifier linearization.
Patricia Desgreys received the M.Sc. degree and Ph.D. in Microelectronics from the University of Bordeaux in 1996 and 1999 respectively. She has been with Institute Mines Telecom - TELECOM ParisTech since 2000. She is currently full professor heading the Circuit and Communication Systems (C2S) research team at the LTCI Laboratory. She is in charge of research on Wireless Systems and Design Techniques for Nanoscale Circuits with special emphasis on Cognitive Radio Systems, Smart AMS Systems for IoT & Cyber-Physical Systems. So far, she has co-authored more than 120 technical publications mainly in international journals and conference proceedings and has been involved in many collaborative projects. Since 2007, she is a member of the Steering Committee (SC) of French research network GdR SOC2 in charge of animating the community of 600 French researchers on SoC design for embedded systems and connected objects. She is involved in the international animation of the CAS community, in particular President of IEEE-CAS France since 2015, member of IEEE NEWCAS Steering Committee since 2011, Technical Program Chair (TPC) of IEEE NEWCAS in 2012 & 2013 and TPC of IEEE ICECS on 2016. She has been Guest Editor of Special Issues in Analog Integrated Circuits and Signal Processing in 2013 & 2014 and she is currently guest editor of the ISICAS special issue in IEEE TCASII journal.